ds1044 4in1 highspeed silicon delay line ds1044 021798 1/6 features ? allsilicon timing circuit ? four independent buffered delays ? initial delay tolerance 1.5 ns ? stable and precise over temperature and voltage ? leading and trailing edge precision preserves the input symmetry ? standard 14pin dip, 14pin soic (150 mil) ? vapor phase, ir and wave solderable ? available in tape and reel pin assignment v cc 12 3 4 5 6 7 1413 12 11 10 98 ncout1 nc out2 out3 out4 in1 nc in2in3 in4 nc gnd ds1044 14pin dip ds1044r 14pin soic (150 mil) see mech. drawings section pin description in1in4 input signals out1out4 output signals nc no connection v cc +5 volt supply gnd ground description the ds1044 series is a 4in1 version of the low power, +5 volt, high speed, ds1035. the ds1044 series of delay lines have four independent logic buffered delays in a single package. the device is dallas semiconductor's fastest 4in1 delay line. it is available in a standard 14pin dip and 14pin soic. the device features precise leading and trailing edge accuracies. it has the inherent reliability of an allsilicon delay line solution. the ds1044's nominal tolerance is 1.5 ns and an additional tolerance over temperature and voltage of 1.0 ns for the faster delays. each output is capable of driving up to 10 ls loads. standard delay values are indicated in table 1. cus- tomers may contact dallas semiconductor at (972) 3714348 for further information. downloaded from: http:///
ds1044 021798 2/6 logic diagram figure 1 time delay in out one of four part number delay table (t plh , t phl ) table 1 part number delay per output (ns) initial tolerance tolerance over (temp and voltage) ds10445 5 1.5 ns 1.0 ns ds10446 6 1.5 ns 1.0 ns ds10447 7 1.5 ns 1.0 ns ds10448 8 1.5 ns 1.0 ns ds104410 10 1.5 ns 1.0 ns ds104412 12 1.5 ns 1.0 ns ds104414 14 1.5 ns 1.5 ns ds104418 18 1.5 ns 1.5 ns ds104420 20 1.5 ns 1.5 ns ds104425 25 2.0 ns 1.5 ns notes: 1. nominal conditions are +25 c and v cc =+5.0 volts. 2. temperature range of 0 c to 70 c and voltage range of 4.75 volts to 5.25 volts. 3. delay accuracy are for both leading and trailing edges. downloaded from: http:///
ds1044 021798 3/6 test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters of the ds1044. the input waveform is produced by a precision pulse gener- ator under software control. time delays are measured by a time interval counter (20 ps resolution) connected to the output. the ds1044 output taps are selected and connected to the interval counter by a vhf switch con- trol unit. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus. ds1044 test circuit figure 2 pulse generator time interval counter start 50 w 50 w stop out outputs 14 unit under test vhf switch control unit 4 inputs downloaded from: http:///
ds1044 021798 4/6 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0 c to 70 c; v cc =+5v 5%) parameter symbol test condition min typ max units supply voltage v cc 4.75 5.00 5.25 v active current i cc v cc =5.25v period=1 m s 45 ma high level input voltage v ih 2.2 v cc +0.5 v low level input voltage v il 0.5 0.8 v input leakage i l 0v< v i < v cc 1.0 1.0 m a high level output current i oh v cc =4.75v v oh =4v 1.0 ma low level output current i ol v cc =4.75v v ol =0.5v 12 ma ac electrical characteristics (+25 c; v cc =5v 5%) parameter symbol min typ max units notes period t period 2 (t wi ) ns 3 input pulse width t wi 100% of tap delay ns 3 inputtotap output delay t plh, t phl table 1 ns output rise or fall time t or , t of 2.0 2.5 ns powerup time t pu 100 ms capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 10 pf downloaded from: http:///
ds1044 021798 5/6 test conditions ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high: 3.0v 0.1v low: 0.0v 0.1v source impedance: 50 w max. rise and fall time: 3.0 ns max. measured between 0.6v and 2.4v. pulse width: 500 ns pulse period: 1 m s output load capacitance: 15 pf output: each output is loaded with the equivalent of one 74f04 input gate. data is measured at the 1.5v level on the rising and falling edges. note: the above conditions are for test only and do not restrict the devices under other data sheet conditions. timing diagram 1.5v 1.5v 1.5v 1.5v 1.5v in t fall t rise 80% 20% t plh t phl out t wi t wi period notes: 1. all voltages are referenced to ground. 2. @ v cc =5 volts and 25 c, delay accuracy on both the rising and falling edges within tolerances given in table 1. 3. pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to decoupling, layout, etc. downloaded from: http:///
ds1044 021798 6/6 terminologyperiod : the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5 volt point on the leading edge and the 1.5 volt point on the trailing edge or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall ( input fall time): the elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. t plh (time delay, rising): the elapsed time between the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse. downloaded from: http:///
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